本計畫以研發3奈米先進製程的材料、製程及元件，以利智慧終端應用中即時的計算之需求。鍺(鍺矽)有比應變矽通道更高的載子遷移率，環繞式電晶體因為具有更優於鰭式電晶體的控制能力，並搭配三維堆疊的架構以提升電流，實現高效能及低功耗的電路。最佳化磊晶、應力源設計與模擬、摻雜設計、閘極堆疊、載子遷移率計算及考慮量子效應之載子分布計算等、並加入鐵電負電容與原子層工程，以完成環繞式通道之電晶體設計。

Ge/GeSi is used for the channels in this project and it is a promising material for 3nm node due to its high mobility. GAA have superior gate control and the ION can be boost by channel stacking. Co-optimization of epitaxy, stressor, doping, gate stack, mobility, carrier distribution, FE material, atomic layer engineering is studied for the device design.